1. Field of the Invention
This invention relates generally to a QAM (Quadrature Amplitude Modulation) demodulator and more specifically to such a demodulator featuring an improved function by which resynchronization can be achieved in a shorter time duration as compared with known QAM demodulators. This invention is highly suited for use in a digital radio transmission system.
2. Description of the Prior Art
A digital radio transmission system is susceptible to multipath fading or the like and invites waveform distortion of the transmitted signal, which degrades signal reception. In order to minimize these problems, it is the current practice to employ a transversal equalizer using a transversal filter.
The transversal equalizer in a digital radio transmission system, however, has encountered the difficulty that distortion of the transmitted signal is apt to exceed the equalizing capability thereof. More specifically, upon the distortion reaching a level at which the equalizer is unable to deal with same, asynchronism of clock and carrier signal in a demodulator is induced and results in asynchronism of the control loop of the transversal filter. These conditions induce signal distortion within the equalizer itself. Therefore, even if the distortion of the transmitted signal again falls within the capability of the equalizer, the synchronized state is not automatically restored in the equalizer. A known approach to solving this problem is to reset the tap gain control signals to their initial values upon the occurrence of asynchronism in the demodulator. This prior art maintains the equalizer at reset until resynchronism of the clock and carrier in the demodulator occurs. Accordingly, as the equalizer remains inoperative during this time period, the control loop of the equalizer is not brought into synchronization unless the waveform distortion of the transmitted signal is lowered to a considerable extent.
The problem of the prior art will further be discussed with reference to FIGS. 1 through 3.
FIG. 1 is a block diagram showing a known 16-QAM demodulator, which generally comprises a transversal equalizer 1 and a demodulator or demodulating section 2 interconnected thereto. The transversal equalizer 1 includes a tap gain control signal generator 3, four adders 5 to 8, four subtracters 9 to 12, a switch 85 and a transversal filter 4. On the other hand, the demodulator 2 includes a coherent detector 13, two 3-bit type of AD (Analog-to-Digital) converters 14 and 15, and a carrier recovery circuit 16. The transversal filter 1 includes a delay circuit with 5 taps and a tap gain controller (both not shown). The transversal filter 1 receives an incoming quadrature-modulated IF (Intermediate Frequency) signal, and reduces or eliminates intersymbol interference involved in the applied signal using tap gain control signals R+1, R-1, R+2, R-2, I+1, I-1, I+2 and I-2. These tap gain control signals are applied to the transversal filter 1 through the switch 85 from the adders 5-8 and subtracters 9-12.
The coherent detector 13 receives the output of the transversal filter 1 and coherently or synchronously demodulates same using a recovered carrier applied thereto from the carrier recovery circuit 16. The reproduced baseband signals (analog) P and Q are applied to the AD converters 14 and 15. The AD converter 14 outputs two data signals D1p, D2p, and an error signal Ep, while the other AD converter 14 outputs two data signals D1q, D2q, an error signal Eq, and a clock signal CLK. The carrier recovery circuit 16 is supplied with D1p, D1q, Ep, Eq, and recovers the carrier which is applied to the coherent detector 13 as above mentioned. On the other hand, the tap gain control signal generator 3 receives all of the outputs of the AD converters 14 and 15, and produces control signals Rp+1, Rp-1, Rp+2, Rp-2, Rq+1, Rq-1, Rq+2, Rq-2, Ip+1, Ip-1, Ip+2, Ip-2, Iq+1, Iq-1, Iq+2 and Iq-2, which undergo addition and subtraction at the next stage and then are applied, as the tap gain control signals R+1 through I+2, to the transversal filter 1 via the switch 85.
The carrier recovery circuit 16 produces a reset signal R which assumes a logic 0 as long as the demodulator 2 is synchronized and which assumes a logic 1 upon the demodulator 2 going out of synchronism. The switch 85 is reset in response to the reset signal R assuming a logic 1. More specifically, the switch 85 prohibits the tap gain control signals R+1 through I-2 to be applied to the transversal filter 1, and begins applying a previously determined constant levels to the transversal filter 1. This means that the transversal equalizer 1 is maintained inoperative while the reset signal R assumes a logic 1.
The principle operation of a transversal equalizer has been described in an article entitled "4/5 GHz 16-QAM 200 mb/s demodulator with transversal equalizer" in the 1984 plenary meeting of The Institute of Electronics Communications Engineers of Japan. Further, the carrier recovery circuit has been disclosed in detail in Japanese Patent Application No. 56-15775.
FIGS. 2A and 2B are block diagrams showing in detail the arrangement of the conventional tap gain control signal generator 3. As shown in FIG. 2A, tapped delay means 17L, 20L, 23L, 26L, 29L and 32L are provided in parallel, each of which includes three one-bit delay lines (17-34). The one-bit delay lines 17, 20, 26 and 29 respectively receives the data signals D1p, D2p, D1q and D2q, while the other one-bit delay lines 23 and 32 receives respectively the error signals Ep and Eq. Each of the delay means 17L, 20L, 23L, 26L, 29L and 32L outputs delayed signals (D1p0, D1p1, D1p2, etc., as shown in the drawing), some of which are applied to exclusive OR gates 37-52 of FIG. 2B and are utilized to generate the above-mentioned tap gain control signals Rp+1 through Ip-2. The operations of the arrangements shown in FIGS. 2A and 2B will be well known to those skilled in the art, so that the further description thereof will be omitted for clarity.
In order to explain in more detail the problem of the prior art, reference is now made to FIG. 3 in which a space diagram of the incoming modulated IF signal is illustrated concurrently with the outputs of the AD converters 14 and 15. In FIG. 3, 16 black circles are arranged in parallel with the orthogonal axes P and Q, and represent respectively normal or standard positions of the incoming message points A1 to A16. It is assumed that the message points A1, A5 and A13 respectively depart from their normal positions to A1', A5' and A13' due to intersymbol interference (viz., the standard message points are deviated in-phase with same polarity). In accordance with this assumption if the demodulator 2 is in synchronism, the deviated message points A1', A5' and A13' remains at their positions, and hence appropriate error signals are generated by which the undesirably deviated message points are able to be restored to their standard positions. On the other hand, if the demodulator 2 is not synchronized, the deviated message point A5' moves along circle M1 and is located at a message point A5" (for example). As a result, this message point A5" is erroneously determined as a message point which is deviated from the nearest message point A1. For this reason the transversal equalizer 1 is reset or rendered inoperative if the demodulator 2 is not synchronized. This control pause of the equalizer continues until the demodulator 2 restores synchronism.
In order to overcome this problem, intermittent resetting of a transversal filter has been proposed in the U.S. Pat. No. 4,567,599 assigned to the same entity as the instant invention. According to this prior art, when asynchronism is detected in a demodulator, a reset signal is intermittently generated to render the transversal filter operative at intervals during a period in which the transversal filter is paused.
The intermittent resetting as above mentioned will further be discussed with reference to FIG. 4, which shows in a block diagram form an arrangement of the carrier recovery circuit 16. The circuit 16 includes a voltage controlled oscillator (VCO) 100, a carrier recovery controller 102, a sine wave generator 104, an adder 106 and a reset signal generator 108. The generator 108 corresponds to an async detector 58 in FIG. 1 of the aforesaid U.S. Pat. No. 4,567,599, and includes four resistors R1, R2, R3 and R4, a capacitor C, a bias voltage source 110 and a comparator 112. The carrier recovery controller 102 receives the data and error signals D1p, D1q, Ep and Eq from the AD converters 14 and 15, and, upon detecting asynchronism in the demodulator 2, forces the sine wave generator 104 to generate a sine wave therefrom by applying an output signal 102a as a trigger signal. The frequency of the sine wave thus obtained should be very low (viz., about few Hz) in order to inspect a frequency for bringing the demodulator into synchronism. The VCO 100 receives the sum of the outputs of the carrier recovery controller 102 and the sine wave generator 104, and slowly changes the output, viz., the recovered carrier's frequency. The output of the VCO 100 is applied to the coherent detector 13. The operation of the closed control loop including the elements 100, 102, 104 and 106 is well known in the art, and hence further description thereof will be omitted for clarity.
On the other hand, according to the prior art such as the aforesaid U.S. Pat. No. 4,567,599, the sine wave generated at the generator 104 is also applied to the reset signal generator 108 and is integrated at an integrator consisting of the resistor R1 and the capacitor C. It should be noted that the time constant of the integrator should be considerably large (viz., few hundreds ms) in order to integrate the sine wave with such a long period. The comparator 112 outputs a logic 0 when the voltage at its inverting input(-) exceeds the voltage applied to its non-inverting input (+). The output of the comparator 112 (logic 1 or 0), viz., the reset signal R, is applied to the switch 85, which corresponds to a reset controller 60 in FIG. 1 of the U.S. Pat. No. 4,567,599. The switch 85 (or the reset controller 60), upon receiving a logic 0 from the carrier recovery circuit 16, initiates intermittent resetting of the transversal filter 4 until a logic 1 is applied to the switch 85 from the reset signal generator 108.
As previously mentioned, the time constant of the integrator (R1 and C) is very large as compared with the carrier frequency. Hence, even if the demodulator 13 is again brought into synchronism by the intermittent resetting, the output of the generator 108 does not change rapidly from a logic 0 to a logic 1 in response to the resynchronism. This means that the known technique has encountered the problem that the demodulator 13 once resynchronized by the intermittent resetting is apt to again fall into asynchronism due to signal distortion which occurs until the reset signal generator 108 outputs a logic 1 in response to the resynchronism. Summing up, this prior art strives to shorten the inoperative duration of the equalizer by discontinuously checking quality recovery of an incoming IF signal through intermittent resetting of the equalizer. However, such an approach fails to solve the drawback arising from the fact that the reset signal generator 108 is slow in response upon the demodulator restoring synchronism, and has proven insufficient to effectively shorten the inoperative period of the equalizer.
The U.S. Pat. No. 4,703,282 assigned to the same entity as the instant invention discloses an improved digital demodulator, wherein a message point of an incoming quadrature-modulated signal is checked as to its location within a signal space diagram. However, this prior does not employ intermittent resetting of a transversal filter while a demodulator is in asynchronism, and hence resynchronization can not be attained in a short time duration as compared with the instant invention.